1. Field of the Invention
The present invention relates to a pattern shape evaluation apparatus, a pattern shape evaluation method, a method of manufacturing a semiconductor device, and a program.
2. Related Background Art
In a conventional technique for evaluating a pattern of a semiconductor device, a pattern width is measured from an acquired pattern image, and the measured value is compared with a preset value, thereby evaluating the pattern. However, when the shape of the pattern is complicated, it is impossible to accurately judge whether the shape of the pattern is abnormal if the pattern width is measured at one point alone. Therefore, the number of measurement points has to be increased, and this decreases the throughput of the measurement.
In order to solve this problem, there has been proposed a technique wherein an allowable range of a pattern shape is preset, and edge data obtained from a pattern image is judged to find whether it is within the allowable range, thereby evaluating the pattern (refer to Japanese Patent laid open (kokai) No. 2005-98885).
The pattern of the semiconductor device tends to be miniaturized, and it is becoming common to form a pattern whose size is equal to or less than an exposure wavelength. Therefore, the more the pattern is miniaturized, the more easily a difference is made between the design data and the actual pattern, and the actual pattern is far more distorted than the shape of the design data. Corner portions of the pattern especially tend to have a greater margin of error with respect to the design data. There is a possibility that the shape of a mask pattern can not be accurately transferred during exposure.
In general, the pattern requires accuracy in, for example, position or width only in some parts, and there occurs no practical problem even if the shape of the pattern is out of the allowable range in other parts. However, since the margin of error in the shape of the pattern becomes greater as described above along with the progress in the miniaturization of the pattern, the shape deviates from the allowable range in parts that are not essentially important, with the result that the pattern is often judged as defective and a manufacture yield is decreased. Japanese Patent laid open (kokai) No. 2005-98885 discloses no solution for such a problem.
On the other hand, there is also disclosed a technique wherein a particular area is specified in a pattern, and the shape of the pattern is evaluated within that area (refer to Japanese Patent laid open (kokai) No. 61(1986)-80011). However, in Japanese Patent laid open (kokai) No. 61(1986)-80011, the area is manually specified, and there is no disclosure or suggestion as to which area in the pattern the evaluation is desirably conducted in, so that accurate evaluation of the pattern shape is not ensured.